1. Field of the Invention
The present invention relates to an insulated-gate bipolar semiconductor device and a method of manufacturing the same.
2. Description of the Prior Art
FIG. 4 is a sectional view showing a conventional insulated-gate bipolar transistor (IGBT). On an upper major surface of a P.sup.+ silicon substrate 1, an N.sup.+ buffer layer 2 and an N.sup.- drain layer 3 are formed in this order by, for example, epitaxial growth. P base regions 4 are formed on a surface of the N.sup.- layer 3 by selective diffusion or the like; and further, N.sup.+ emitter regions 5 are formed in each of the P base regions 4 by selective diffusion or the like. On a region 11 between the P regions 4 adjacent to each other in the N.sup.- drain layer 3, a gate electrode 8 is formed with interposition of a gate oxidation film 7, extending near the N.sup.+ emitter regions 5. An emitter electrode 9 is provided on both the N.sup.+ emitter regions 5 and the P.sup.+ base region 4 lying between the N.sup.+ emitter regions 5, in ohmic contact. On a lower major surface of the P.sup.+ substrate 1, a collector electrode 10 is provided in ohmic contact.
Now, the operation of the IGBT will be simply described. When voltage which is higher to some extent than the emitter potential is applied to a gate electrode 8 with forward bias voltage applied between the emitter electrode 9 and the collector electrode 10, a channel region 6 lying between each of the N.sup.+ emitter regions 5 and N.sup.- drain layer 3 and located just under the gate electrode 8 is inverted to the N-type. Then, electrons move from the N.sup.+ emitter region 5 through the channel region 6 into the N.sup.- drain layer 3. In accord with it, holes move from the P.sup.+ substrate 1 through the N.sup.+ buffer layer 2 into the N.sup.- drain layer 3, and eventually, the emitter electrode 9 and the collector electrode 10 become conductive with each other.
It is desirable that voltage between the emitter electrode 9 and the collector electrode which are conductive with each other (referred to as "ON-voltage" hereinafter) is low, but to reduce the ON voltage, it is necessary to make the design by which current passing through the region 11 to the N.sup.- drain layer 3 in the vertical direction can flow more easily there. Especially, this is imperative necessity because a resistively of the N.sup.- drain layer 3 rises when the carrier lifetime is shortened in the N.sup.- drain layer 3 by putting lifetime killer in to implement a high-speed operation of the IGBT.
To make the current flow more easily through the region 11 in the vertical direction, for example, the width l of the region 11 is made wider or the impurity in the region 11 is increased to make an N.sup.+ region 12, so as to reduce a value R of the resistance there (FIG. 5). However, making the width l too large or making the resistance value R too small, the withstand voltage retained while the device turns off is reduced. Specifically, depletion layers expand from the P base regions 4 into the N.sup.- layer 3 with an increase in forward bias; however, when the width l is small, the depletion layers from opposite sides join together at a relatively low voltage to moderate the electric field around, as shown by the broken line in FIG. 6A. Meanwhile, when the width l is large, the depletion layers do not easily join as shown in FIG. 6B, much more concentration of the electric field around the region 11 is caused, and the device is broken down. When the resistance value R becomes too small, the same phenomenon leads to a decline of the withstand voltage.
Thus, in the conventional IGBT, there arises the problem that it is difficult to reduce ON-voltage without reducing the withstand voltage.